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r07ds0201ej0100 rev.1.00 page 1 of 15 jan 25, 2011 preliminary datasheet r2j20656anp integrated driver - mos fet (drmos) description the r2j20656anp multi-chip module inco rporates a high-side mos fet, low-side mos fet, and mos-fet driver in a single qfn package. the on and off timing of the powe r mos fet is optimized by the built-in driver, making this device suitable for large-current buck converters. the chip also incorporates a high-side bootstrap switch, eliminating the need for an external sbd for this purpose. features ? compliant with intel 6 ? 6 drmos specification. ? built-in power mos fet suitable for note book, desktop, server application. ? low-side mos fet with built-in sbd for lower loss and reduced ringing. ? built-in driver circuit whic h matches the power mos fet ? built-in tri-state input function which ca n support a number of pwm controllers ? high-frequency operation (above 1 mhz) possible ? vin operating-voltage range: 27 vmax ? large average output current (max.35 a) ? achieve low power dissipation ? controllable driver: remote on/off ? zero current detection for a diode emulation operation ? double thermal protection: thermal warning & thermal shutdown ? built-in bootstrapping switch ? small package: qfn40 (6 mm ? 6 mm ? 0.95 mm) ? pb-free/halogen-free outline integrated driver-mos fet (drmos) qfn40 package 6 mm 6 mm (bottom view) low-side mos pad high-side mos pad driver pad 40 11 0 30 21 11 31 20 vin gh boot vcin disbl# zcd_en# cgnd vdrv gl pgnd thwn pwm mos fet driver vswh r07ds0201ej0100 rev.1.00 jan 25, 2011
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 2 of 15 jan 25, 2011 block diagram boot gh gl cgnd vdrv 2 a cgnd driver chip high side mos fet low side mos fet vdrv 160 k vcin 20 k 35 k vswh pgnd vin disbl# zcd_en# pwm level shifter vcin uvl vcin input logic (ttl level) (3 state in) thwn thdn thwn cgnd overlap protection. & logic boot sw zero current det. notes: 1. truth table for the disbl# pin 2. truth table for the zcd_en# pin disbl# input driver chip status "l" shutdown (gl, gh = "l") "open" shutdown (gl, gh = "l") "h" enable (gl, gh = "active") zcd_en# input driver chip status "l" "diode emulation mode" "open" "continuous conduction mode" "h" "continuous conduction mode" 3. output signal from the uvl block 4. output signal from the thwn block "h" "l" uvl output logic level vcin vh vl for active for shutdown "h" "l" thermal warning logic level t ic (c) twarnh twarnl thermal warning normal operating 5. truth table for the thdn block driver ic temp. driver chip status < 150c enable (gl, gh = "active") > 150c shutdown (gl, gh = "l") (latch-off)
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 3 of 15 jan 25, 2011 pin arrangement (top view) vswh vin pwm disbl# thwn cgnd gl vswh vswh vswh vswh vin vin vin vswh pgnd pgnd pgnd pgnd pgnd vswh vin cgnd 21 22 23 24 25 26 27 28 29 30 1098765432 1 20 11 12 13 14 15 16 17 18 19 31 40 39 38 37 36 35 34 33 32 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd vswh vswh vin vin vin vswh gh cgnd boot vdrv vcin zcd_en# note: all die-pads (three pads in total) should be soldered to pcb. pin description pin name pin no. description remarks zcd_en# 1 zero current detection enable when asserted "l" signal, zero crossing detection is enabled vcin 2 control input voltage (+5 v input) driver vcc input vdrv 3 gate supply voltage (+5 v input) 5 v gate drive boot 4 bootstrap voltage pin to be s upplied +5 v through internal switch cgnd 5, 37, pad control signal ground should be connected to pgnd externally gh 6 high-side gate signal pin for monitor vin 8 to 14, pad input voltage vswh 7, 15, 29 to 35, pad phase output/switch output pgnd 16 to 28 power ground gl 36 low-side gate signal pin for monitor thwn 38 thermal warning thermal warning when over 115c disbl# 39 signal disable disabled when disbl# is "l". this pin is pulled low when internal ic over the thermal shutdown level, 150c. pwm 40 pwm drive logic input 5 v logic input
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 4 of 15 jan 25, 2011 absolute maximum ratings (ta = 25c) item symbol rating units note pt(25) 25 power dissipation pt(110) 8 w 1 average output current iout 35 a vin(dc) ?0.3 to +27 2 input voltage vin(ac) 30 v 2, 4 supply voltage & drive voltage vcin & vdrv ?0.3 to +6 v 2 vswh(dc) 27 2 switch node voltage vswh(ac) 30 v 2, 4 vboot(dc) 32 2 boot voltage vboot(ac) 36 v 2, 4 i/o voltage vpwm, vdisble, vlsdbl, vthwn ?0.3 to vcin + 0.3 v 2, 5 thwn/thdn current ithwn, ithdn 0 to 1.0 ma operating junction temperatur e tj-opr ?40 to +150 c storage temperature tstg ?55 to +150 c notes: 1. pt(25) represents a pcb tem perature of 25c, and pt (110) represents 110 ?c. 2. rated voltages are relative to voltages on the cgnd and pgnd pins. 3. for rated current, (+) indicates inflow. 4. the specification values indica ted "ac" are limited within 10 ns. 5. vcin + 0.3 v < 6 v 0 25 50 75 100 125 150 175 pcb temperature (c) safe operating area 0 5 10 15 20 25 30 35 40 45 average output current (a) vout = 1.3 v vin = 12 v vcin = 5 v l = 0.45 h fsw = 1 mhz
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 5 of 15 jan 25, 2011 recommended operating condition item symbol rating units note input voltage vin 4.5 to 22 v supply voltage & drive voltage vcin & vdrv 4.5 to 5.5 v electrical characteristics (ta = 25c, vcin = 5 v, vdrv = 5 v, vswh = 0 v, unless otherwise specified) item symbol min typ max units test conditions vcin start threshold v h 4.1 4.3 4.5 v vcin shutdown threshold v l 3.6 3.8 4.0 v uvlo hysteresis duvl ? 0.5 ? v v h ? v l vcin operating current i cin ? 49 ? ma f pwm = 1 mhz, ton_pwm = 120 ns supply vcin disable current i cin-disbl ? ? 150 ? a disbl# = 0 v, pwm = zcd_en# = open pwm input high level v h-pwm 4.0 ? ? v 5.0 v pwm interface pwm input low level v l-pwm ? ? 0.8 v pwm input resistance r in-pwm 6.5 12.5 25 k ? pwm = 1 v pwm input tri-state range v in-tri 1.5 ? 3.2 v 5.0 v pwm interface pwm input shutdown hold-off time t hold-off * 1 ? 150 ? ns enable level v enbl 2.0 ? ? v disable level v disbl ? ? 0.8 v input current i disbl ? 2.0 5.0 ? a disbl# = 1 v disbl# input thdn on resistance r thdn * 1 0.2 0.5 1.0 k ? disbl# = 0.2 v zcd disable level vzcddisbl 2.0 ? ? v zcd enable level vzcden ? ? 0.8 v zcd_en# input current izcden ?52 ?25 ?12 ? a zcd_en# = 1 v warning temperature t thwn * 1 100 115 130 c driver ic temperature temperature hysteresis t hys * 1 ? 15 ? c thwn on resistance r thwn * 1 0.2 0.5 1.0 k ? thwn = 0.2 v thermal warning thwn leakage current i leak ? ? 1.0 ? a thwn = 5 v thermal shutdown shutdown temperature tstdn * 1 130 150 ? c driver ic temperature note: 1. reference values for design. not 100% tested in production.
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 6 of 15 jan 25, 2011 typical application vcin cgnd gl vin boot 4.5 to 22 v +5 v +1.3 v gh vdrv r2j20656 anp pgnd thwn disbl# zcd_en# pwm1 pwm vswh vcin cgnd gl vin boot gh vdrv r2j20656 anp pgnd thwn disbl# zcd_en# pwm2 pwm vswh vcin cgnd gl vin boot gh vdrv r2j20656 anp pgnd thwn disbl# zcd_en# pwm vswh vcin cgnd gl vin boot gh vdrv pwm control circuit r2j20656 anp pgnd thwn disbl# zcd_en# pwm vswh pwm3 pwm4 power gnd signal gnd
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 7 of 15 jan 25, 2011 pin connection +5 v 0.1 f 0.45 h vin (4.5 to 22 v) pgnd pgnd power gnd signal gnd r2j20656anp cgnd pad 21 22 23 24 25 26 27 28 29 30 10 9 8 7 654321 20 11 12 13 14 15 16 17 18 19 31 40 39 38 37 36 35 34 33 32 pwm disbl# thwn cgnd vswh vin vswh gl pgnd pgnd vswh vin vswh gh cgnd boot vdrv vcin zcd_en# zcd_en#able signal input vin pad pgnd 1.0 f cgnd cgnd 10 f 4 +5 v thermal shutdown pwm input vswh pad 10 k +5 v 10 k vout thermal warning 0 to 10
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 8 of 15 jan 25, 2011 test circuit vcin vin vswh boot gl r2j20656anp pgnd gh vcont vinput cgnd disbl# vdrv zcd_en# pwm 5 v pulse note: p in = i in v in + i cin v cin p out = i o v o efficiency = p out / p in p loss (drmos) = p in ? p out ta = 27c average output voltage v o v v v cin v in i cin v i in a a i o electric load averaging circuit
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 9 of 15 jan 25, 2011 typical data power loss vs. output current output current (a) output voltage (v) power loss (w) normalized power loss @ vin = 12 v input voltage (v) power loss vs. input voltage power loss vs. switching frequency normalized power loss @ vout = 1.3 v switching frequency (khz) normalized power loss @ f pwm = 600 khz power loss vs. output voltage 0 1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 30 35 4 6 8 10 20 12 14 22 16 18 0.8 0.9 1.0 1.1 1.2 1.4 1.6 1.3 1.5 1.7 0.8 0.9 1.0 1.1 1.2 1.3 1.5 1.7 1.4 1.6 0.8 0.9 1.0 1.1 1.2 1.3 1.5 1.7 1.4 1.6 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 250 500 750 1000 1250 vin = 12 v vcin = vdrv = 5 v vout = 1.3 v f pwm = 600 khz l = 0.45 h vin = 12 v vcin = vdrv = 5 v f pwm = 600 khz l = 0.45 h iout = 25 a vin = 12 v vcin = vdrv = 5 v vout = 1.3 v l = 0.45 h iout = 25 a vcin = vdrv = 5 v vout = 1.3 v f pwm = 600 khz l = 0.45 h iout = 25 a
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 10 of 15 jan 25, 2011 power loss vs. output inductance output inductance (h) normalized power loss @ l = 0.45 h normalized power loss @ vcin = vdrv = 5 v power loss vs. vcin 0.10.20.30.40.50.60.70.80.91.0 vcin = vdrv (v) 4.5 5.0 5.5 6.0 vin = 12 v vcin = vdrv = 5 v vout = 1.3 v f pwm = 600 khz iout = 25 a vin = 12 v vcin = vdrv = 5 v vout = 1.3 v l = 0.45 h iout = 0 a switching frequency (khz) average icin vs. switching frequency average icin (ma) 10 20 40 50 30 70 60 250 500 750 1000 1250 0.8 0.9 1.0 1.1 1.2 1.3 1.5 1.7 1.4 1.6 0.8 0.9 1.0 1.1 1.2 1.3 1.5 1.7 1.4 1.6 vin = 12 v vout = 1.3 v f pwm = 600 khz l = 0.45 h iout = 25 a
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 11 of 15 jan 25, 2011 description of operation the drmos multi-chip module incorporates a high-side mo s fet, low-side mos fet, and mos-fet driver in a single qfn package. since the parasitic in ductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. the control timing between the high-side mos fet, low- side mos fet, and driver is optimized so that high efficiency can be obtain ed at low output-voltage. vcin & disbl# the vcin pin is connected to the uvl (under-voltage lockout) module, so that the driver is disabled as long as vcin is 4.3 v or less. on cancellation of uvl, the driver remain s enabled until the uvl input is driven to 3.8 v or less. the signal on pin disbl# also enables or disables the circuit. voltages from ?0.3 v to vcin can be applied to the disbl# pin, so on/off control by a logic ic or the use of a resistor, etc., to pull the disbl# line up to vcin are both possible. vcin disbl# driver state l ? disable (gl, gh = l) h l disable (gl, gh = l) h h active h open disable (gl, gh = l) the pulled-down mos fet, which is turned on when internal ic temperature becomes over thermal shutdown level, is connected to the disbl# pin. the detailed function is described in thdn section. pwm & zcd_en# the pwm pin is the signal input pin for the driver chip. the input-voltage range is ?0.3 v to (vcin + 0.3 v). when the pwm input is high, the gate of the high -side mos fet (gh) is high and the gate of the lo w-side mos fet (gl) is low. pwm gh gl l l h h h l the zcd_en# pin is the zero current detection operation enable pin for "diode emulation mode (dem)" when zcd_en# is low. this function improves light load efficiency by preventing negative inductor current from output capacitor. driver ic monitors inductor cu rrent and when inductor cu rrent crosses zero, driver ic turn off low side mos fet automatically. figure 1.1 shows the typical high side and low side gate switching and inductor current (il) during continuous conduction mode (ccm), and figure 1.2 shows dem when asserting zero current detection enable signal. zcd_en# pin is internally pulled up to vcin with 160 k ? resistor. when zero current detection function is not used, keep this pin open or pulled up to vcin. ccm operation (zcd_en# = "h" or open mode) il gh pwm gl figure 1.1 typical signals during ccm
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 12 of 15 jan 25, 2011 dem operation (zcd_en# = "l" in light load condition) gl il gh pwm 0 a figure 1.2 typical signals during dem the pwm input is ttl level and has hysteresis. when the signal route from the control ic is high impedance, the tri- state function turns off the high- and lo w-side mos fets. this function operates when the pwm input signal stays in the input hysteresis window for 150 ns (typ.). after the tri-state mode has been entered and gh and gl have become low, a pwm input voltage of 4.0 v or more is required to make the circuit return to normal operation. 3.2 v 1.5 v 3.2 v 1.5 v 150 ns (t hold-off ) 150 ns (t hold-off ) 150 ns (t hold-off ) 150 ns (t hold-off ) pwm gh gh gl gl pwm figure 2 pwm shutdown-hold time signal
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 13 of 15 jan 25, 2011 the equivalent circuit for the pwm-pin input is shown in the next figure. m1 is in the on state during normal operation; after the pwm input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection signal has been driven high, the transistor m1 is turned off. when vcin is powered up, m1 is star ted in the off state regardless of pwm low or open state. after pwm is asserted high signal, m1 becomes on and shifts to normal operation. vcin 14.5 k to internal control tri-state detection signal 12.5 k input logic m1 pwm pin figure 3 equivalent circuit for the pwm-pin input thwn & thdn this device has two level thermal detection, one is thermal warning and the other is thermal shutdown function. this thermal warning feature is the indi cation of the high temperature status. thwn is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k ? ) to thwn for systems with the thermal warning implementation. when the chip temperature of the in ternal driver ic becomes over 115c, thermal warning function operates. this signal is only indication for the system c ontroller and does not disable drmos operation. when thermal warning function is not used, keep this pin open. t ic (c) 115 100 thermal warning normal operating thwn output logic level "l" "h" figure 4 thwn trigger temperature
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 14 of 15 jan 25, 2011 thdn is an internal thermal shutdown signal when driver ic becomes over 150c. this function makes high side mos fet and low side mos fet turn off for the device protection from abnormal high temperature situation and at the same time disbl# pi n is pulled low internally to give notice to the system controller. once thermal shutdown function operates, dr iver ic keeps disbl# pin pulled low until vcin becomes under uvl level (3.8 v). figure 5 shows the example of two types of disbl# connection with the system controller signal. driver ic temp. driver chip status < 150c enable (gl, gh = "active") > 150c shutdown (gl, gh = "l") figure 5.1 thdn signal to the system controller figure 5.2 on/off signal from the system controlle r 2 a 10 k 5 v disbl# thermal shutdown detection to internal logic to shutdown signal 2 a disbl# thermal shutdown detection to internal logic on/off signal 10 k mos fet the mos fets incorporated in r2j20656anp are highly suitable for synchronous-rectification buck conversion. for the high-side mos fet, the drain is connected to the vin pin and the source is connected to the vswh pin. for the low-side mos fet, the drain is connected to the vswh pin and the source is c onnected to th e pgnd pin.
r2j20656anp preliminary r07ds0201ej0100 rev.1.00 page 15 of 15 jan 25, 2011 package dimensions dimension in millimeters reference symbol p-hvqfn40-p-0606-0.50 ? ? pvqn0040ke-a mass[typ.] renesas code jeita package code previous code 5.95 6.00 6.05 5.95 6.00 6.05 d min nom max e e 0.87 0.89 0.91 a2 ? ? 0.20 0.865 0.91 0.95 f a 0.005 0.02 0.04 a1 0.17 0.22 0.27 0.16 0.20 0.24 b b1 ? 0.50 ? 0.40 0.50 0.60 ? ? 0.05 lp x ? ? 0.05 y ? ? 0.20 ? ? 0.20 y1 t 6.15 6.20 6.25 hd 6.15 6.20 6.25 ? 0.75 ? he zd ? 0.75 ? ze 0.06 0.10 0.14 0.17 0.20 0.23 l1 c1 0.17 0.22 0.27 c2 l1 c2 lp a2 a1 a he/2 e / 2 e he t s ab b x s ab e zd f s ab x 4 x 4 ze 2-a section hd/2 d /2 d hd 4-c0.50 20 20 4-(0.139) 1.95 1.95 1.95 1.95 y s 1pin 40 1pin 40 c0.3 index 0.2 0.7 2.2 2.05 0.2 2.2 0.2 2.2 2.2 2.05 cav no. die no. b s y1 s 0.69 a b ordering information part name quantity shipping container r2j20656anp#g0 2500 pcs taping reel
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